This invention relates to a central processor-controlled, interrupt-driven data communications system for transferring data between a computer and various peripheral devices in which no interrupt context switch is required. The invention also relates to a central processor-controlled, interrupt-driven data communications system in a computer in which data can be continuously written into or read from noncontiguous pages of memory space without causing an interrupt context switch.
In a typical central processor-controlled data communications system within a computer, the central processing unit of the computer controls data communications between the memory of the computer and a plurality of input/output (I/O) devices such as printers, keyboards, other computers, etc. This central processor-controlled system is in contrast to other non-central processor-controlled communications systems in which a plurality of processors jointly control data communications between I/O devices and the memory of the computer. An example of such a non-central processor-controlled system is direct-memory access. In direct-memory access (DMA), a plurality of DMA processors each associated with a respective I/O device compete with the central processing unit of the computer for access to the memory to transfer data between I/O devices and the memory of the computer. This type of DMA system is essentially a network in which each of the DMA processors and the central processing unit of the computer can independently obtain use of the memory bus. In the type of system of the present invention, only the central processing unit can obtain control of bus to read from or write to the memory. Any I/O devices needing to access the memory must transmit an interrupt to the central processing unit. The CPU will then stop what it is doing and will execute the memory transfer requested by the I/O device. Thus, in this central processor-controlled system, only the central processing unit has direct access to the memory, and the I/O devices do not.
In the operation of a typical central processor-controlled system in a computer, in order to access the memory of the computer, an I/O device must generate an interrupt, which is an electronic signal that is transmitted to the central processing unit and causes it to temporarily halt the operation on which it is working and execute the memory transfer requested by the I/O device. Interrupts, which are well-known and used universally in computer systems, cause the central processing unit of the computer to perform an "interrupt context switch."
An interrupt context switch is the saving to memory of the general purpose registers of the computer so that the general purpose registers may be used by the computer program which performs the memory transfer. A typical computer has a single bank of general purpose registers which are used by a number of various computer programs being executed by the computer. When an interrupt is generated, the computer saves the contents of the register bank to memory so that interrupt service routine can use the general purpose registers. After the interrupt service routine is finished being executed, the original contents of the register bank are retrieved from memory and restored so that the original program can begin to be executed where it left off without losing any of its data. This saving to memory and the subsequent retrieval of general purpose registers is referred to as an "interrupt context switch" for the purposes of this specification.
When an interrupt is generated in a typical prior art computer, the contents of the general purpose registers are saved to the memory. Next, the interrupt service routine associated with the interrupt is performed. There are typically a number of different interrupt service routines within a computer, each being associated with a different type of interrupt. Each interrupt typically includes an address that tells the central processing unit of the computer where to find the correct interrupt service routine associated with the particular interrupt generated. The interrupt service routine, which is typically a computer program, is executed and performs the task requested by the interrupt. During its execution, the interrupt service routine uses the general purpose registers whose contents were previously saved to memory. After the interrupt service routine is finished being executed, the original contents of the general purpose registers are restored from memory, and the execution of the computer program that was interrupted by the interrupt resumes.
It is undesirable to perform an interrupt context switch each time an interrupt is generated because of the time required to save the contents of all of the general purpose registers to memory. The time required to transfer data between a register in the central processing unit and the memory of a computer is relatively long, usually taking on the order of five times as long as a data transfer between two registers in the central processing unit. The time required for typical state-of-the-art computers today to execute an interrupt context switch and the associated interrupt service routine is approximately 100-140 microseconds. As a result, the execution of an interrupt context switch each time an interrupt is generated can critically affect the performance of a computer, especially in data communications, in which a great number of interrupts are required by a computer needing to handle a relatively large number of data transfers between its memory and peripheral devices. In these days of dramatically increased data communications, many computers are brought to their knees due to the need to perform an interrupt context switch each time an interrupt is generated.
One approach to eliminating the problem of performing an interrupt context switch each time an interrupt is generated involved using a number of memory locations for the storage of information relating to the interrupt generated. In this approach, when an interrupt was generated, the interrupt would provide the central processing unit of the computer with an address specifying a memory location. The memory location contained a particular input or output instruction, which would then be executed by the central processing unit to accomplish the task requested by the interrupt. Thus, the input or output instruction was analogous to an interrupt service routine. The memory of the computer included many memory locations, each of which was associated with a respective interrupt, and each of the memory locations stored the input or output instruction that would properly service its associated interrupt. While this approach obviated the need to perform an interrupt context switch, the memory still needed to be accessed in order to fetch the input and output instructions that were to be executed by the central processing unit to service the interrupts. Although this approach resulted in better computer performance over the typical approaches which executed interrupt context switches, the relatively long memory access times required to fetch the input and output instructions in this approach unduly hindered the performance of the computer.
The memory of a computer is typically divided into "pages," each page of the memory consisting of the same number of memory locations, for example, 1000 memory locations. Thus, a computer may have a memory consisting of 1000 pages of memory, each page having 1000 memory locations, for one megabyte of total memory storage. Due to the longer access times required for memory, data is typically transferred to or from the memory a page at a time instead of a memory location at a time.
Before a data file is transferred into the memory of a typical prior art computer, the computer first finds an empty memory page into which the data can be transferred. This is accomplished by accessing an available page table. Such a table includes the memory addresses of all memory pages that are not currently being used to store data. The computer accesses the available page table to retrieve the memory address of an empty memory page, and then uses that address to access the memory and store the data file into the empty memory page.
In order to retrieve data, a reverse process is used. Before a data file can be retrieved from memory, the computer must first determine where that file was stored in memory. This is accomplished by accessing an existing file table, which includes a list of all the data files currently being stored by the memory and their addresses. The computer searches the existing file table for the desired file, and then retrieves the memory address where the file is stored.
Two factors complicate this process of storing and retrieving data files from memory. First, many data files are longer than a single memory page, and they may require many memory pages to be completely stored. Second, in order to utilize the memory as fully as possible, a data file may be split up and stored in a number of noncontiguous portions of memory, each portion consisting of one or more memory pages. For example, a data file that is ten memory pages long may have its first portion consisting of three pages of data stored at memory locations 2000-5000, its second portion consisting of four pages of data stored at memory locations 9000-13,000, and its final three pages of data stored at memory locations 15,000-18,000.
This ability of a computer to write a data file to a plurality of noncontiguous blocks of memory is referred to as "scatter-write," and the ability to read a data file from noncontiguous blocks of memory is referred to as "gather-read." In order to facilitate multi-page data files, a typical available page table groups together contiguous available memory pages under a single address. As a result, a multi-page data file may be stored in memory by accessing the available page table only once if there is a contiguous block of memory available that is at least as large as the data file to be stored. If the data file is required to be stored in two noncontiguous blocks of memory, then the available page table must be accessed twice. If the data file is required to be stored in three noncontiguous blocks of memory, then the available page table must be accessed three times, and so on.
In the scatter-write method in a typical prior art computer, when a data file needs to be written to the memory, an interrupt is generated and an interrupt context switch performed, and then the available page table is accessed a first time in order to retrieve the address of the first data block available in the memory. After the first portion of the data file is transferred to the memory, another interrupt is generated and the associated interrupt context switch performed, and the available page table is accessed again to get the address of the next available block of memory. This process continues until the data file has been completely written to the memory. Since an interrupt context switch is performed each time that the available page table is accessed, the associated time required for processing the interrupt hinders the performance of the computer, especially when intensive data communications are involved.
In the typical gather-read method of retrieving a data file from memory, the existing file table may have several addresses associated with a single data file. Each of the addresses specifies a particular noncontiguous memory block. In order to retrieve a file, an interrupt is generated and the existing file table is accessed to retrieve the memory address of the first portion of the data file to be retrieved. After that portion is retrieved, another interrupt is generated and the existing file table is accessed again to retrieve the memory address of the next noncontiguous portion of the memory in which the data file is stored. This process continues, an interrupt being generated each time the existing file table is accessed, until the entire data file is retrieved from memory. This method also unduly hinders the performance of the computer since an interrupt is generated each time the existing file table is accessed.